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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">VTCR_EL2, Virtualization Translation Control Register</h1><p>The VTCR_EL2 characteristics are:</p><h2>Purpose</h2>
        <p>The control register for stage 2 of the EL1&amp;0 translation regime.</p>
      <h2>Configuration</h2><p>AArch64 System register VTCR_EL2 bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-vtcr.html">VTCR[31:0]</a>.</p>
        <p>If EL2 is not implemented, this register is <span class="arm-defined-word">RES0</span> from EL3.</p>

      
        <p>This register has no effect if EL2 is not enabled in the current Security state.</p>
      <h2>Attributes</h2>
        <p>VTCR_EL2 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="19"><a href="#fieldset_0-63_45">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-44_44-1">HAFT</a></td><td class="lr" colspan="2"><a href="#fieldset_0-43_42">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-41_41-1">TL0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-40_40-1">GCSH</a></td><td class="lr" colspan="1"><a href="#fieldset_0-39_39">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-38_38-1">D128</a></td><td class="lr" colspan="1"><a href="#fieldset_0-37_37-1">S2POE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-36_36-1">S2PIE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-35_35-1">TL1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-34_34-1">AssuredOnly</a></td><td class="lr" colspan="1"><a href="#fieldset_0-33_33-1">SL2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-32_32-1">DS</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">RES1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_30-1">NSA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-29_29-1">NSW</a></td><td class="lr" colspan="1"><a href="#fieldset_0-28_28-1">HWU62</a></td><td class="lr" colspan="1"><a href="#fieldset_0-27_27-1">HWU61</a></td><td class="lr" colspan="1"><a href="#fieldset_0-26_26-1">HWU60</a></td><td class="lr" colspan="1"><a href="#fieldset_0-25_25-1">HWU59</a></td><td class="lr" colspan="2"><a href="#fieldset_0-24_23">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-22_22-1">HD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-21_21-1">HA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19-1">VS</a></td><td class="lr" colspan="3"><a href="#fieldset_0-18_16">PS</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_14">TG0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-13_12">SH0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-11_10">ORGN0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-9_8">IRGN0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-7_6-1">SL0</a></td><td class="lr" colspan="6"><a href="#fieldset_0-5_0">T0SZ</a></td></tr></tbody></table><div class="text_before_fields">
    <p>Unless stated otherwise, any of the bits in VTCR_EL2 are permitted to be cached in a TLB.</p>
  </div><h4 id="fieldset_0-63_45">Bits [63:45]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-44_44-1">HAFT, bit [44]<span class="condition"><br/>When FEAT_HAFT is implemented:
                        </span></h4><div class="field"><p>Hardware managed Access Flag for Table descriptors.</p>
<p>Enables the Hardware managed Access Flag for Table descriptors.</p><table class="valuetable"><tr><th>HAFT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Hardware managed Access Flag for Table descriptors is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Hardware managed Access Flag for Table descriptors is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-44_44-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-43_42">Bits [43:42]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-41_41-1">TL0, bit [41]<span class="condition"><br/>When FEAT_THE is implemented:
                        </span></h4><div class="field">
      <p>Control bit to check for presence of MMU TopLevel0 permission attribute.</p>
    <table class="valuetable"><tr><th>TL0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This bit does not have any effect on stage 2 translations.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Enables MMU TopLevel0 permission attribute check for TTBR0_EL1 and TTBR1_EL1 translations.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-41_41-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-40_40-1">GCSH, bit [40]<span class="condition"><br/>When FEAT_THE is implemented and FEAT_GCS is implemented:
                        </span></h4><div class="field">
      <p>Assured stage 1 translations for Guarded control stacks. Enforces use of the AssuredOnly attribute in stage 2 for the memory accessed by privileged Guarded control stack data accesses.</p>
    <table class="valuetable"><tr><th>GCSH</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For the memory accessed by privileged Guarded control stack data accesses, the AssuredOnly attribute in stage 2 is not required to be set.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For the memory accessed by privileged Guarded control stack data accesses, the AssuredOnly attribute in stage 2 is required to be set.</p>
        </td></tr></table>
      <p>This bit is permitted to be cached in a TLB.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-40_40-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-39_39">Bit [39]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-38_38-1">D128, bit [38]<span class="condition"><br/>When FEAT_D128 is implemented:
                        </span></h4><div class="field">
      <p>Enables VMSAv9-128 translation system for stage 2 translation.</p>
    <table class="valuetable"><tr><th>D128</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Translation system follows VMSA-64 translation process.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Translation system follows VMSAv9-128 translation process.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-38_38-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-37_37-1">S2POE, bit [37]<span class="condition"><br/>When FEAT_S2POE is implemented:
                        </span></h4><div class="field">
      <p>Enable Permission Overlay. Enables permission overlay in stage 2 Permission model.</p>
    <table class="valuetable"><tr><th>S2POE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Overlay disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Overaly enabled.</p>
        </td></tr></table>
      <p>This bit is not permitted to be cached in a TLB.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-37_37-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-36_36-1">S2PIE, bit [36]<span class="condition"><br/>When FEAT_S2PIE is implemented:
                        </span></h4><div class="field">
      <p>Select Permission Model. Enables usage of permission indirection in stage 2 Permission model.</p>
    <table class="valuetable"><tr><th>S2PIE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Direct permission model.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Indirect permission model.</p>
        </td></tr></table>
      <p>This field is <span class="arm-defined-word">RES1</span> when VTCR_EL2.D128 is set.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-36_36-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-35_35-1">TL1, bit [35]<span class="condition"><br/>When FEAT_THE is implemented:
                        </span></h4><div class="field">
      <p>Control bit to check for presence of MMU TopLevel1 permission attribute.</p>
    <table class="valuetable"><tr><th>TL1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This bit does not have any effect on stage 2 translations.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Enables MMU TopLevel1 permission attribute check for TTBR0_EL1 and TTBR1_EL1 translations.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-35_35-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-34_34-1">AssuredOnly, bit [34]<span class="condition"><br/>When FEAT_THE is implemented:
                        </span></h4><div class="field">
      <p>AssuredOnly attribute enable for VMSAv8-64. Configures use of bit[58] of the stage 2 translation table Block or Page descriptor.</p>
    <table class="valuetable"><tr><th>AssuredOnly</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Bit[58] of each stage 2 translation Block or Page descriptor does not indicate AssuredOnly attribute.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Bit[58] of each stage 2 translation Block or Page descriptor indicates AssuredOnly attribute.</p>
        </td></tr></table>
      <p>This field is <span class="arm-defined-word">RES0</span> when <a href="AArch64-vtcr_el2.html">VTCR_EL2</a>.D128 is 1.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-34_34-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-33_33-1">SL2, bit [33]<span class="condition"><br/>When FEAT_LPA2 is implemented and (FEAT_D128 is not implemented or VTCR_EL2.D128 == 0):
                        </span></h4><div class="field"><p>Starting level of the stage 2 translation lookup controlled by VTCR_EL2.</p>
<p>If VTCR_EL2.DS == 1, then VTCR_EL2.SL2, in combination with VTCR_EL2.SL0, gives encodings for the stage 2 translation table walk initial lookup level.</p>
<p>If VTCR_EL2.DS == 0, then VTCR_EL2.SL2 is <span class="arm-defined-word">RES0</span>.</p>
<p>If the translation granule size is not 4KB, then this field is <span class="arm-defined-word">RES0</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-33_33-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-32_32-1">DS, bit [32]<span class="condition"><br/>When FEAT_LPA2 is implemented and (FEAT_D128 is not implemented or VTCR_EL2.D128 == 0):
                        </span></h4><div class="field">
      <p>This field affects whether a 52-bit output address can be described by the translation tables of the 4KB or 16KB translation granules.</p>
    <table class="valuetable"><tr><th>DS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>Bits[49:48] of translation descriptors are <span class="arm-defined-word">RES0</span>.</p>
<p>Bits[9:8] in Block and Page descriptors encode shareability information in the SH[1:0] field. Bits[9:8] in Table descriptors are ignored by hardware.</p>
<p>The minimum value of VTCR_EL2.T0SZ is 16. Any memory access using a smaller value generates a stage 2 level 0 translation table fault.</p>
<p>The minimum value of <a href="AArch64-vstcr_el2.html">VSTCR_EL2</a>.T0SZ is 16. Any memory access using a smaller value generates a stage 2 level 0 translation table fault.</p>
<p>Output address[51:48] is 0000.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>Bits[49:48] of translation descriptors hold output address[49:48].</p>
<p>Bits[9:8] in translation descriptors hold output address[51:50].</p>
<p>The shareability information of Block and Page descriptors for cacheable locations is determined by VTCR_EL2.SH0.</p>
<p>The minimum value of VTCR_EL2.T0SZ is 12. Any memory access using a smaller value generates a stage 2 level 0 translation table fault.</p>
<p>The minimum value of <a href="AArch64-vstcr_el2.html">VSTCR_EL2</a>.T0SZ is 12. Any memory access using a smaller value generates a stage 2 level 0 translation table fault.</p>
<div class="note"><span class="note-header">Note</span><p>As <span class="xref">FEAT_LPA</span> must be implemented if VTCR_EL2.DS == 1, the minimum values of VTCR_EL2.T0SZ and <a href="AArch64-vstcr_el2.html">VSTCR_EL2</a>.T0SZ are 12, as determined by that extension.</p></div><p>For the TLBI range instructions affecting IPA, the format of the argument is changed so that bits[36:0] hold BaseADDR[52:16]. For the 4KB translation granule, bits[15:12] of BaseADDR are treated as 0000. For the 16KB translation granule, bits[15:14] of BaseADDR are treated as 00.</p>
<div class="note"><span class="note-header">Note</span><p>This forces alignment of the ranges used by the TLBI range instructions.</p></div></td></tr></table>
      <p>This field is <span class="arm-defined-word">RES0</span> for a 64KB translation granule.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-32_32-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_31">Bit [31]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-30_30-1">NSA, bit [30]<span class="condition"><br/>When FEAT_SEL2 is implemented:
                        </span></h4><div class="field">
      <p>Non-secure stage 2 translation output address space for the Secure EL1&amp;0 translation regime.</p>
    <table class="valuetable"><tr><th>NSA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>All stage 2 translations for the Non-secure IPA space of the Secure EL1&amp;0 translation regime access the Secure PA space.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>All stage 2 translations for the Non-secure IPA space of the Secure EL1&amp;0 translation regime access the Non-secure PA space.</p>
        </td></tr></table><p>This bit behaves as 1 for all purposes other than reading back the value of the bit when one of the following is true:</p>
<ul>
<li>The value of VTCR_EL2.NSW is 1.
</li><li>The value of <a href="AArch64-vstcr_el2.html">VSTCR_EL2</a>.SA is 1.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-30_30-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-29_29-1">NSW, bit [29]<span class="condition"><br/>When FEAT_SEL2 is implemented:
                        </span></h4><div class="field">
      <p>Non-secure stage 2 translation table address space for the Secure EL1&amp;0 translation regime.</p>
    <table class="valuetable"><tr><th>NSW</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>All stage 2 translation table walks for the Non-secure IPA space of the Secure EL1&amp;0 translation regime are to the Secure PA space.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>All stage 2 translation table walks for the Non-secure IPA space of the Secure EL1&amp;0 translation regime are to the Non-secure PA space.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-29_29-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-28_28-1">HWU62, bit [28]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[62] of the stage 2 translation table Block or Page entry.</p>
    <table class="valuetable"><tr><th>HWU62</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Bit[62] of each stage 2 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Bit[62] of each stage 2 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-28_28-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-27_27-1">HWU61, bit [27]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[61] of the stage 2 translation table Block or Page entry.</p>
    <table class="valuetable"><tr><th>HWU61</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Bit[61] of each stage 2 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Bit[61] of each stage 2 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-27_27-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-26_26-1">HWU60, bit [26]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[60] of the stage 2 translation table Block or Page entry.</p>
    <table class="valuetable"><tr><th>HWU60</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Bit[60] of each stage 2 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Bit[60] of each stage 2 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-26_26-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-25_25-1">HWU59, bit [25]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[59] of the stage 2 translation table Block or Page entry.</p>
    <table class="valuetable"><tr><th>HWU59</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Bit[59] of each stage 2 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Bit[59] of each stage 2 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-25_25-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-24_23">Bits [24:23]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-22_22-1">HD, bit [22]<span class="condition"><br/>When FEAT_HAFDBS is implemented:
                        </span></h4><div class="field">
      <p>Hardware management of dirty state in stage 2 translations when EL2 is enabled in the current Security state.</p>
    <table class="valuetable"><tr><th>HD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Stage 2 hardware management of dirty state disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Stage 2 hardware management of dirty state enabled, only if the VTCR_EL2.HA bit is also set to 1.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-22_22-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-21_21-1">HA, bit [21]<span class="condition"><br/>When FEAT_HAFDBS is implemented:
                        </span></h4><div class="field">
      <p>Hardware Access flag update in stage 2 translations when EL2 is enabled in the current Security state.</p>
    <table class="valuetable"><tr><th>HA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Stage 2 Access flag update disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Stage 2 Access flag update enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-21_21-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-20_20">Bit [20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_19-1">VS, bit [19]<span class="condition"><br/>When FEAT_VMID16 is implemented:
                        </span></h4><div class="field">
      <p>VMID Size.</p>
    <table class="valuetable"><tr><th>VS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>8-bit VMID. The upper 8 bits of <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a> are ignored by the hardware, and treated as if they are all zeros, for every purpose except when reading back the register.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>16-bit VMID. The upper 8 bits of <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a> are used for allocation and matching in the TLB.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-19_19-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-18_16">PS, bits [18:16]</h4><div class="field">
      <p>Physical address Size for the second stage of translation.</p>
    <table class="valuetable"><tr><th>PS</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b000</td><td>
          <p>32 bits, 4GB.</p>
        </td></tr><tr><td class="bitfield">0b001</td><td>
          <p>36 bits, 64GB.</p>
        </td></tr><tr><td class="bitfield">0b010</td><td>
          <p>40 bits, 1TB.</p>
        </td></tr><tr><td class="bitfield">0b011</td><td>
          <p>42 bits, 4TB.</p>
        </td></tr><tr><td class="bitfield">0b100</td><td>
          <p>44 bits, 16TB.</p>
        </td></tr><tr><td class="bitfield">0b101</td><td>
          <p>48 bits, 256TB.</p>
        </td></tr><tr><td class="bitfield">0b110</td><td>
          <p>52 bits, 4PB.</p>
        </td></tr><tr><td class="bitfield">0b111</td><td>
          <p>56 bits, 64PB.</p>
        </td><td>When FEAT_D128 is implemented</td></tr></table><p>All other values are reserved.</p>
<p>The reserved values behave in the same way as the <span class="binarynumber">0b101</span> or <span class="binarynumber">0b110</span> encoding, but software must not rely on this property as the behavior of the reserved values might change in a future revision of the architecture.</p>
<p>If the translation granule is not 64KB and <span class="xref">FEAT_LPA2</span> is not implemented, the value <span class="binarynumber">0b110</span> is treated as reserved.</p>
<p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether an implementation that does not implement <span class="xref">FEAT_LPA</span> supports setting the value of <span class="binarynumber">0b110</span> for the 64KB translation granule size or whether setting this value behaves as the <span class="binarynumber">0b101</span> encoding.</p>
<p>In an implementation that supports 52-bit PAs, if the value of this field is not <span class="binarynumber">0b110</span> or a value treated as <span class="binarynumber">0b110</span>, then bits[51:48] of every translation table base address for the stage of translation controlled by VTCR_EL2 are <span class="binarynumber">0b0000</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_14">TG0, bits [15:14]</h4><div class="field">
      <p>Granule size for the <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a>.</p>
    <table class="valuetable"><tr><th>TG0</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>4KB.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>64KB.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>16KB.</p>
        </td></tr></table><p>Other values are reserved.</p>
<p>If <span class="xref">FEAT_GTG</span> is implemented, <a href="AArch64-id_aa64mmfr0_el1.html">ID_AA64MMFR0_EL1</a>.{TGran4_2, TGran16_2, TGran64_2} indicate which granule sizes are supported for stage 2 translation.</p>
<p>If <span class="xref">FEAT_GTG</span> is not implemented, <a href="AArch64-id_aa64mmfr0_el1.html">ID_AA64MMFR0_EL1</a>.{TGran4, TGran16, TGran64} indicate which granule sizes are supported.</p>
<p>If the value is programmed to either a reserved value or a size that has not been implemented, then the hardware will treat the field as if it has been programmed to an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> choice of the sizes that has been implemented for all purposes other than the value read back from this register.</p>
<p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the value read back is the value programmed or the value that corresponds to the size chosen.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-13_12">SH0, bits [13:12]</h4><div class="field">
      <p>Shareability attribute for memory associated with translation table walks using <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a> or <a href="AArch64-vsttbr_el2.html">VSTTBR_EL2</a>.</p>
    <table class="valuetable"><tr><th>SH0</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Non-shareable.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Outer Shareable.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Inner Shareable.</p>
        </td></tr></table>
      <p>Other values are reserved. The effect of programming this field to a Reserved value is that behavior is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-11_10">ORGN0, bits [11:10]</h4><div class="field">
      <p>Outer cacheability attribute for memory associated with translation table walks using <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a> or <a href="AArch64-vsttbr_el2.html">VSTTBR_EL2</a>.</p>
    <table class="valuetable"><tr><th>ORGN0</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Normal memory, Outer Non-cacheable.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-9_8">IRGN0, bits [9:8]</h4><div class="field">
      <p>Inner cacheability attribute for memory associated with translation table walks using <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a> or <a href="AArch64-vsttbr_el2.html">VSTTBR_EL2</a>.</p>
    <table class="valuetable"><tr><th>IRGN0</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Normal memory, Inner Non-cacheable.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-7_6-1">SL0, bits [7:6]<span class="condition"><br/>When FEAT_TTST is implemented and (FEAT_D128 is not implemented or VTCR_EL2.D128 == 0):
                        </span></h4><div class="field">
      <p>Starting level of the stage 2 translation lookup, controlled by VTCR_EL2. The meaning of this field depends on the value of VTCR_EL2.TG0.</p>
    <table class="valuetable"><tr><th>SL0</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td><p>If VTCR_EL2.TG0 is <span class="binarynumber">0b00</span> (4KB granule):</p>
<ul>
<li>
<p>If <span class="xref">FEAT_LPA2</span> is not implemented, start at level 2.</p>

</li><li>
<p>If <span class="xref">FEAT_LPA2</span> is implemented and VTCR_EL2.SL2 is <span class="binarynumber">0b0</span>, start at level 2.</p>

</li><li>
<p>If <span class="xref">FEAT_LPA2</span> is implemented and VTCR_EL2.SL2 is <span class="binarynumber">0b1</span>, start at level -1.</p>

</li></ul>
<p>If VTCR_EL2.TG0 is <span class="binarynumber">0b10</span> (16KB granule) or <span class="binarynumber">0b01</span> (64KB granule), start at level 3.</p></td></tr><tr><td class="bitfield">0b01</td><td><p>If VTCR_EL2.TG0 is <span class="binarynumber">0b00</span> (4KB granule):</p>
<ul>
<li>
<p>If <span class="xref">FEAT_LPA2</span> is not implemented, start at level 1.</p>

</li><li>
<p>If <span class="xref">FEAT_LPA2</span> is implemented and VTCR_EL2.SL2 is <span class="binarynumber">0b0</span>, start at level 1.</p>

</li><li>
<p>If <span class="xref">FEAT_LPA2</span> is implemented, the combination of VTCR_EL2.SL0 == 01 and VTCR_EL2.SL2 == 1 is reserved.</p>

</li></ul>
<p>If VTCR_EL2.TG0 is <span class="binarynumber">0b10</span> (16KB granule) or <span class="binarynumber">0b01</span> (64KB granule), start at level 2.</p></td></tr><tr><td class="bitfield">0b10</td><td><p>If VTCR_EL2.TG0 is <span class="binarynumber">0b00</span> (4KB granule):</p>
<ul>
<li>
<p>If <span class="xref">FEAT_LPA2</span> is not implemented, start at level 0.</p>

</li><li>
<p>If <span class="xref">FEAT_LPA2</span> is implemented and VTCR_EL2.SL2 is <span class="binarynumber">0b0</span>, start at level 0.</p>

</li><li>
<p>If <span class="xref">FEAT_LPA2</span> is implemented, the combination of VTCR_EL2.SL0 == 10 and VTCR_EL2.SL2 == 1 is reserved.</p>

</li></ul>
<p>If VTCR_EL2.TG0 is <span class="binarynumber">0b10</span> (16KB granule) or <span class="binarynumber">0b01</span> (64KB granule), start at level 1.</p></td></tr><tr><td class="bitfield">0b11</td><td><p>If VTCR_EL2.TG0 is <span class="binarynumber">0b00</span> (4KB granule):</p>
<ul>
<li>
<p>If <span class="xref">FEAT_LPA2</span> is not implemented, start at level 3.</p>

</li><li>
<p>If <span class="xref">FEAT_LPA2</span> is implemented and VTCR_EL2.SL2 is <span class="binarynumber">0b0</span>, start at level 3.</p>

</li><li>
<p>If <span class="xref">FEAT_LPA2</span> is implemented, the combination of VTCR_EL2.SL0 == 11 and VTCR_EL2.SL2 == 1 is reserved.</p>

</li></ul>
<p>If VTCR_EL2.TG0 is <span class="binarynumber">0b10</span> (16KB granule) and <span class="xref">FEAT_LPA2</span> is implemented, start at level 0.</p></td></tr></table>
      <p>If this field is programmed to a value that is not consistent with the programming of VTCR_EL2.T0SZ, then a stage 2 level 0 Translation fault is generated.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-7_6-2"><span class="condition"><br/>When FEAT_TTST is not implemented and (FEAT_D128 is not implemented or VTCR_EL2.D128 == 0):
                        </span></h4><div class="field">
      <p>Starting level of the stage 2 translation lookup, controlled by VTCR_EL2. The meaning of this field depends on the value of VTCR_EL2.TG0.</p>
    <table class="valuetable"><tr><th>SL0</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>If VTCR_EL2.TG0 is <span class="binarynumber">0b00</span> (4KB granule), start at level 2. If VTCR_EL2.TG0 is <span class="binarynumber">0b10</span> (16KB granule) or <span class="binarynumber">0b01</span> (64KB granule), start at level 3.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>If VTCR_EL2.TG0 is <span class="binarynumber">0b00</span> (4KB granule), start at level 1. If VTCR_EL2.TG0 is <span class="binarynumber">0b10</span> (16KB granule) or <span class="binarynumber">0b01</span> (64KB granule), start at level 2.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>If VTCR_EL2.TG0 is <span class="binarynumber">0b00</span> (4KB granule), start at level 0. If VTCR_EL2.TG0 is <span class="binarynumber">0b10</span> (16KB granule) or <span class="binarynumber">0b01</span> (64KB granule), start at level 1.</p>
        </td></tr></table>
      <p>All other values are reserved. If this field is programmed to a reserved value, or to a value that is not consistent with the programming of VTCR_EL2.T0SZ, then a stage 2 level 0 Translation fault is generated.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-7_6-3"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-5_0">T0SZ, bits [5:0]</h4><div class="field"><p>The size offset of the memory region addressed by <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a>. The region size is 2<sup>(64-T0SZ)</sup> bytes.</p>
<p>The maximum and minimum possible values for T0SZ depend on the level of translation table and the memory translation granule size, as described in <span class="xref">'The AArch64 Virtual Memory System Architecture'</span>.</p>
<p>If this field is programmed to a value that is not consistent with the programming of SL0, then a stage 2 level 0 Translation fault is generated.</p>
<div class="note"><span class="note-header">Note</span><p>For the 4KB translation granule, if <span class="xref">FEAT_LPA2</span> is implemented and this field is less than 16, the translation table walk begins with a level -1 initial lookup.</p><p>For the 16KB translation granule, if <span class="xref">FEAT_LPA2</span> is implemented and this field is less than 17, the translation table walk begins with a level 0 initial lookup.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing VTCR_EL2</h2>
        <p>Unless stated otherwise, any of the bits in VTCR_EL2 are permitted to be cached in a TLB.</p>
      <p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, VTCR_EL2</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0010</td><td>0b0001</td><td>0b010</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV&gt; == '11' then
        X[t, 64] = NVMem[0x040];
    elsif EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    X[t, 64] = VTCR_EL2;
elsif PSTATE.EL == EL3 then
    X[t, 64] = VTCR_EL2;
                </p><h4 class="assembler">MSR VTCR_EL2, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0010</td><td>0b0001</td><td>0b010</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV&gt; == '11' then
        NVMem[0x040] = X[t, 64];
    elsif EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    VTCR_EL2 = X[t, 64];
elsif PSTATE.EL == EL3 then
    VTCR_EL2 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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